VHDL报错std_logic type does not match integer literal
随风飘扬 学习 2015年12月01日7:07 5651
VHDL报错std_logic type does not match integer literal
library ieee;
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use ieee.std_logic_1164.all;
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entity f_adder2 is
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port(a,b,c : in std_logic; so,co : out std_logic);
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end entity f_adder2;
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architecture bhv of f_adder2 is
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signal s : std_logic_vector(2 downto 0);
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begin s<=c&b&a;
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process(c,b,a) begin
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case (s) is
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when "000" => so<=0;co<=0;
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when "001" => so<=1;co<=0;
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when "010" => so<=1;co<=0;
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when "011" => so<=0;co<=1;
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when "100" => so<=1;co<=0;
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when "101" => so<=0;co<=1;
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when "110" => so<=0;co<=1;
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when "111" => so<=1;co<=1;
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when others =>NULL;
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end case;
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end process;
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end architecture;
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定义的s是std_logic类型,但你赋值的时候由于没加单引号,被认为是integer类型了,所以应加单引号
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